Freescale Semiconductor MPC8260 Handbücher

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Freescale semiconductor MPC8260 Bedienungsanleitung (1360 Seiten)

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Inhaltsverzeichnis

MPC8260 PowerQUICC™ II

Family Reference Manual

How to Reach Us:

Contents

Freescale Semiconductor xlv

Freescale Semiconductor xlvii

Freescale Semiconductor xlix

Freescale Semiconductor li

Freescale Semiconductor liii

Freescale Semiconductor lv

Freescale Semiconductor lvii

Freescale Semiconductor lix

Freescale Semiconductor lxi

Number Title

Freescale Semiconductor lxiii

Freescale Semiconductor lxv

Freescale Semiconductor lxvii

Freescale Semiconductor lxix

Freescale Semiconductor lxxi

Freescale Semiconductor lxxv

About This Book

Table i. Changes to

, Rev. 1

Audience

Organization

Freescale Semiconductor lxxxi

I-4 Freescale Semiconductor

Chapter 1

1-2 Freescale Semiconductor

Freescale Semiconductor 1-3

1-4 Freescale Semiconductor

Freescale Semiconductor 1-5

1.2 Architecture Overview

100

1.2.1 G2 Core

101

1-8 Freescale Semiconductor

102

Freescale Semiconductor 1-9

103

1.3.1 Signals

104

Freescale Semiconductor 1-11

105

1.5 Serial Protocol Table

106

1.6.1 Pin Configurations

107

1.6.2 Serial Performance

107

1.7 Application Examples

108

Overview

109

1.7.1.4 Cellular Base Station

111

1.7.2 Bus Configurations

113

1.7.2.4 PCI

115

1.7.2.5 PCI with 155-Mbps ATM

116

1-24 Freescale Semiconductor

118

Chapter 2

119

Freescale Semiconductor 2-3

121

2-4 Freescale Semiconductor

122

2.2.1 Instruction Unit

123

2.2.4.1 Integer Unit (IU)

124

2.2.4.3 Load/Store Unit (LSU)

124

2.2.5 Completion Unit

125

2.3 Programming Model

126

2.3.1.1 PowerPC Register Set

127

0 1 2 3 4 678910 1112 1415

129

G2 Core Reference Manual

132

2-16 Freescale Semiconductor

134

2.4 Cache Implementation

135

2.4.1 PowerPC Cache Model

136

Freescale Semiconductor 2-19

137

2.4.2.2 Instruction Cache

138

2.4.2.3 Cache Locking

138

2.5 Exception Model

139

G2 Core

140

Reference Manual

140

MPC603e User’s Manual

141

2.6 Memory Management

143

2-26 Freescale Semiconductor

144

2.7 Instruction Timing

145

Chapter 3

147

Memory Map

147

Configuration and Reset

171

Acronyms and Abbreviations

172

Chapter 4

173

System Interface Unit (SIU)

173

4.1.1 Bus Monitor

175

4.1.2 Timers Clock

175

4.1.3 Time Counter (TMCNT)

176

4.2 Interrupt Controller

179

4.2.1 Interrupt Configuration

180

4.2.1.2 INT Interrupt

181

Freescale Semiconductor 4-13

185

4.3 Programming Model

189

FCCs and MCCs

191

Figure 4-14. SIPNR_H

193

Figure 4-15. SIPNR_L

194

Figure 4-16. SIMR_H

195

Figure 4-17. SIMR_L

195

0123456789101112131415

198

16 17 18 19 20 21 22 23 24 31

198

Figure 4-22. PPC_ACR

201

Figure 4-23. PPC_ALRH

202

Figure 4-24. PPC_ALRL

203

Figure 4-25. LCL_ACR

203

Figure 4-26. LCL_ALRH

204

Figure 4-27. LCL_ALRL

205

4.3.4 PCI Control Registers

220

4.4 SIU Pin Multiplexing

221

Chapter 5

223

5.1.1 Reset Actions

224

5.1.2 Power-On Reset Flow

224

5.1.3 HRESET Flow

225

5.1.4 SRESET Flow

225

16 25 26 27 28 29 30 31

226

5.3 Reset Mode Register (RMR)

227

5.4 Reset Configuration

228

. As Figure 5-7

234

Freescale Semiconductor 5-13

235

5-14 Freescale Semiconductor

236

Part III

237

The Hardware Interface

237

Conventions

238

Chapter 6

241

External Signals

241

6.2 Signal Descriptions

242

Table 6-1. External Signals

243

Chapter 7

257

60x Signals

257

7.1 Signal Configuration

258

7.2 Signal Descriptions

258

Freescale Semiconductor 7-3

259

7.2.1.2 Bus Grant (BG)

260

7.2.2.1 Transfer Start (TS)

261

7.2.3.1 Address Bus (A[0–31])

262

Freescale Semiconductor 7-7

263

7.2.4.3 Transfer Burst (TBST)

264

7.2.4.4 Global (GBL)

264

Freescale Semiconductor 7-9

265

7.2.5.2 Address Retry (ARTRY)

266

7.2.6.1 Data Bus Grant (DBG)

267

7.2.7 Data Transfer Signals

268

Freescale Semiconductor 7-15

271

7-16 Freescale Semiconductor

272

Freescale Semiconductor 7-17

273

7-18 Freescale Semiconductor

274

Chapter 8

275

The 60x Bus

275

8.2 Bus Configuration

276

8.2.2 60x-Compatible Bus Mode

277

8.3 60x Bus Protocol Overview

278

8.3.1 Arbitration Phase

279

8-6 Freescale Semiconductor

280

8.4 Address Tenure Operations

281

8.4.2 Address Pipelining

282

Regarding Table 8-2:

285

Table 8-5. Burst Ordering

288

Figure 8-7. Retry Cycle

297

8.4.5 Pipeline Control

298

8.5 Data Tenure Operations

299

8.5.2 Data Streaming Mode

300

8.7 Processor State Signals

305

8.8 Little-Endian Mode

306

Chapter 9

307

PCI Bridge

307

9.1 Signals

309

9.2 Clocking

309

9.3 PCI Bridge Initialization

309

9.4 SDMA Interface

309

9.7 60x Bus Masters

310

9.9 PCI Interface

311

9.9.1 PCI Interface Operation

312

9-8 Freescale Semiconductor

314

9.9.1.3 Bus Transactions

315

9-12 Freescale Semiconductor

318

9.9.1.4 Other Bus Operations

319

9-14 Freescale Semiconductor

320

9-16 Freescale Semiconductor

322

9.9.1.5 Error Functions

323

9.9.2 PCI Bus Arbitration

325

9.9.2.3 Master Latency Timer

326

9.10 Address Map

327

9.10.2 Address Translation

330

9.10.3 SIU Registers

332

9.11 Configuration Registers

333

9.11.1.1 Message Unit (I

336

O) Registers

336

Table 9-6. describes POCMRx

338

a minimum of

339

Table 9-16. PITAR

348

Table 9-17. PIBAR

349

Table 9-18. describes PICMRx

350

9.11.2.1 Vendor ID Register

352

9.11.2.2 Device ID Register

353

(PIMMRBAR)

359

Table 9-33. GPLABAR

361

9.11.2.20 PCI Bus MIN GNT

363

9.11.2.21 PCI Bus MAX LAT

364

Freescale Semiconductor 9-63

369

9.12 Message Unit (I

371

Table 9-46. IMR

372

9.12.2 Door Bell Registers

373

9.12.3 I

375

9.12.3.2 Inbound FIFOs

376

9.12.3.3 Outbound FIFOs

380

9.12.3.4 I

383

O Registers

383

9.13 DMA Controller

391

9.13.1.1 DMA Direct Mode

392

9.13.1.2 DMA Chaining Mode

392

9.13.1.3 DMA Coherency

393

9.13.1.5 DMA Transfer Types

393

9.13.1.6 DMA Registers

394

Table 9-66. DMAMR

395

IOS interface and before it

395

Channels

395

Table 9-67. DMASR

397

9.14 Error Handling

403

9.14.1.3 PCI Interface

404

Freescale Semiconductor 9-99

405

9.14.1.4 Embedded Utilities

406

Chapter 10

407

Clocks and Power Control

407

2 (DFBRG + 1)

408

10.4.2 Skew Elimination

409

10.4.3 PCI Bridge Clocking

409

10.5 Clock Dividers

411

10.7 PLL Pins

412

.25µm (HiP4) Silicon

413

× (PLLDF + 1) – 1

416

10.10 Basic Power Structure

417

10-12 Freescale Semiconductor

418

Chapter 11

419

Memory Controller

419

11.1 Features

421

11.2 Basic Architecture

422

11.2.2 Page Hit Checking

425

11-8 Freescale Semiconductor

426

and LWR)

427

11.2.8 Atomic Bus Operation

427

11.2.9 Data Pipelining

427

11-10 Freescale Semiconductor

428

Table 11-1. Number of PSDVAL

429

11.3 Register Descriptions

430

11.3.1 Base Registers (BR

431

Table 11-4. BR

432

11.3.2 Option Registers (OR

433

Table 11-5. OR

434

Table 11-6. OR

436

Figure 11-9. OR

437

—UPM Mode

437

)—UPM Mode

437

Figure 11-11. Machine

444

Mode Registers (M

444

MR) (continued)

446

11.4 SDRAM Machine

451

PRECHARGE-ALL-BANKS command

453

CBR REFRESH commands

453

11.4.5 Bank Interleaving

455

Freescale Semiconductor 11-39

457

11-40 Freescale Semiconductor

458

Freescale Semiconductor 11-41

459

Figure 11-26. EAMUX = 1

460

11.4.7 SDRAM Interface Timing

461

11-44 Freescale Semiconductor

462

Freescale Semiconductor 11-45

463

11-46 Freescale Semiconductor

464

11.4.10 SDRAM Refresh

465

11.4.11 SDRAM Refresh Timing

466

ACTIVATE Command

467

READ/WRITE Command

467

11.5.1 Timing Configuration

471

11.5.1.3 Relaxed Timing

474

[29–30] = 00, Fastest Timing)

477

[29–30] = 01)

478

[29–30] = 10)

479

11.6.1 Requests

482

RUN commands (MxMR[OP]

483

RUN Command

485

11.6.4 The RAM Array

487

11.6.4.1 RAM Words

488

Table 11-37. M

494

MR Loop Field Usage

494

11.6.4.4 Signals Negation

496

11.6.4.5 The Wait Mechanism

496

ACTIVATE command

498

Figure 11-74. Exception Cycle

507

11-90 Freescale Semiconductor

508

11.8.2 Slow Devices Example

519

SDRAM, BADDR is not needed

523

Chapter 12

525

Secondary (L2) Cache Support

525

12.1.2 Write-Through Mode

526

Freescale Semiconductor 12-3

527

12.1.3 ECC/Parity Mode

528

Freescale Semiconductor 12-5

529

12.4 L2 Cache Operation

531

12.5 Timing Example

531

Chapter 13

533

IEEE 1149.1 Test Access Port

533

13.2 TAP Controller

534

13.3 Boundary Scan Register

535

13.4 Instruction Register

537

13.6 Nonscan Chain Operation

539

13-8 Freescale Semiconductor

540

Intended Audience

541

IV-2 Freescale Semiconductor

542

Suggested Reading

543

Architecture Documentation

543

IV-8 Freescale Semiconductor

548

Chapter 14

549

14-2 Freescale Semiconductor

550

14.3.2 Features

552

14.3.3 CP Block Diagram

553

14.3.4 G2 Core Interface

554

14.3.5 Peripheral Interface

555

14.3.6 Execution from RAM

556

14.4 Command Set

560

0 1 5 6 10 11 15

561

16 17 18 25 26 27 28 31

561

14.4.1.1 CP Commands

562

14.5 Dual-Port RAM

565

14.5.2 Parameter RAM

568

Table 14-10. Parameter RAM

569

14.6 RISC Timer Tables

570

012 11 12 15

572

SET TIMER Command

573

SET TIMER command

574

Freescale Semiconductor 14-27

575

14-28 Freescale Semiconductor

576

Chapter 15

577

Figure 15-1. SI Block Diagram

578

15.1 Features

579

15.2 Overview

580

Freescale Semiconductor 15-7

583

15.4 Serial Interface RAM

584

15.4.3 Programming SI

586

RAM Entries

586

Table 15-1. SI

587

RAM Entry (MCC = 0)

587

Table 15-2. SI

589

RAM Entry (MCC = 1)

589

15.4.4 SI

590

RAM Programming Example

590

Freescale Semiconductor 15-15

591

Figure 15-9. Example: SI

592

RAM Size

592

15.5.2 SI Mode Registers (SI

593

Table 15-5. SI

594

MR Field Descriptions

594

FSD = 01

597

FSD = 00

598

15.5.3 SI

599

0 1 3 4 5 7 8 9 11 12 13 15

600

15.6.1 IDL Interface Example

602

Figure 15-23. IDL Bus Signals

604

Table 15-10. SI

605

Figure 15-24. GCI Bus Signals

607

Table 15-11. GCI Signals

607

15-32 Freescale Semiconductor

608

15.7.2.2 SCIT Programming

609

15-34 Freescale Semiconductor

610

Chapter 16

611

CPM Multiplexing

611

16.1 Features

612

Freescale Semiconductor 16-3

613

16.3 NMSI Configuration

614

Figure 16-3. Bank of Clocks

615

16.4 CMX Registers

617

16-10 Freescale Semiconductor

620

Chapter 17

631

Baud-Rate Generators (BRGs)

631

Table 17-1. BRGC

633

17.3 UART Baud Rate Examples

635

BRGCx[CD] = 389

636

Chapter 18

637

18-2 Freescale Semiconductor

638

18.2.1 Cascaded Mode

639

0 7 8 9 10 11 12 13 14 15

642

0 13 14 15

644

Chapter 19

645

19-2 Freescale Semiconductor

646

19.2 SDMA Registers

647

19.3 IDMA Emulation

649

19.4 IDMA Features

649

19.5 IDMA Transfers

650

19.5.1.2 Normal Mode

653

19-10 Freescale Semiconductor

654

Freescale Semiconductor 19-11

655

19-12 Freescale Semiconductor

656

19.6 IDMA Priorities

657

19.7 IDMA Interface Signals

657

19.7.1.1 Level-Sensitive Mode

658

19.7.2 DONE

659

19.8 IDMA Operation

660

19.8.2 IDMA

661

Parameter RAM

661

Table 19-4. IDMA

662

DCM is undefined at reset

663

(DMA_WRAP)

664

19.8.3 IDMA Performance

667

19.8.5 IDMA BDs

668

START_IDMA Command

671

STOP_IDMA Command

672

START_IDMA command is issued

674

(on 60x)–IDMA3

676

(PCI-to-60x)—IDMA1

677

(on 60x)–IDMA3 (continued)

677

Chapter 20

679

20.1 Features

680

Figure 20-3 shows GSMR_L

683

20.3 SCC Parameter RAM

691

20.3.1 SCC Base Addresses

692

Table 20-6. RFCR

693

Table 20-7. SCC

694

20.3.4 Initializing the SCCs

695

20.3.7 Reconfiguring the SCCs

702

20.3.8 Saving Power

703

20-26 Freescale Semiconductor

704

Chapter 21

705

SCC UART Mode

705

21.1 Features

706

21.2 Normal Asynchronous Mode

706

21.3 Synchronous Mode

707

21.4 SCC UART Parameter RAM

707

21.7 SCC UART Commands

710

21.10 Hunt Mode (Receiver)

713

STOP TRANSMIT command. The

714

Table 21-8. Reception Errors

716

Freescale Semiconductor 21-15

719

Chapter 22

729

SCC HDLC Mode

729

22.4 SCC HDLC Parameter RAM

731

22.6 SCC HDLC Commands

733

Table 22-4. Transmit Errors

734

Table 22-5. Receive Errors

734

RxBDs are used in receiving

737

Freescale Semiconductor 22-15

743

22-16 Freescale Semiconductor

744

22.15.1 HDLC Bus Features

746

22.15.4 Delayed RTS Mode

748

L1RXD CTSL1TXD

749

22-22 Freescale Semiconductor

750

Chapter 23

751

SCC BISYNC Mode

751

23.1 Features

752

23.4 SCC BISYNC Parameter RAM

753

23.5 SCC BISYNC Commands

754

Table 23-2. Transmit Commands

755

Table 23-3. Receive Commands

755

Transmit Errors

760

Receive Errors

760

Figure 23-6. SCC BISYNC RxBD

762

RESET BCS

767

Freescale Semiconductor 23-19

769

23-20 Freescale Semiconductor

770

Chapter 24

771

SCC Transparent Mode

771

24-2 Freescale Semiconductor

772

24.4.3 End of Frame Detection

775

24.7 SCC Transparent Commands

776

Table 24-4. Receive Commands

777

Table 24-5. Transmit Errors

777

Table 24-6. Receive Errors

778

Descriptions

779

Freescale Semiconductor 24-13

783

24-14 Freescale Semiconductor

784

Chapter 25

785

SCC Ethernet Mode

785

25.2 Features

786

Freescale Semiconductor 25-3

787

25-6 Freescale Semiconductor

790

25.9 SCC Ethernet Commands

793

Table 25-2. Transmit Commands

794

Table 25-3. Receive Commands

794

25.11 Hash Table Algorithm

796

25.12 Interpacket Gap Time

796

25.13 Handling Collisions

796

Ethernet mode register

798

25.18 SCC Ethernet Receive BD

800

25-22 Freescale Semiconductor

806

Freescale Semiconductor 25-23

807

25-24 Freescale Semiconductor

808

Chapter 26

809

SCC AppleTalk Mode

809

26.2 Features

810

26.3 Connecting to AppleTalk

810

26.4.1 Programming the GSMR

811

26.4.2 Programming the PSMR

812

26.4.3 Programming the TODR

812

Chapter 27

813

27.1 Features

814

27.2.3 SMC Parameter RAM

817

CLOSE RXBD command

819

27.2.4.5 Switching Protocols

821

27.3 SMC in UART Mode

822

27.3.1 Features

823

27.3.6 Sending a Break

824

27.3.7 Sending a Preamble

825

27.3.9 SMC UART RxBD

825

Figure 27-6. SMC UART RxBD

826

Figure 27-7. RxBD Example

828

27.3.10 SMC UART TxBD

829

Freescale Semiconductor 27-19

831

27.4 SMC in Transparent Mode

832

Freescale Semiconductor 27-21

833

27-22 Freescale Semiconductor

834

ENTER HUNT MODE

836

27.4.8 SMC Transparent RxBD

838

27.4.9 SMC Transparent TxBD

839

27.5 The SMC in GCI Mode

842

27.5.4 SMC GCI Commands

844

0123 78 15

845

01 78 131415

846

27-36 Freescale Semiconductor

848

Chapter 28

849

28.1 MCC Operation Overview

850

28.2 Global MCC Parameters

852

Figure 28-2. TSTATE High Byte

855

Figure 28-3. INTMSK Mask Bits

856

28.3.1.1

860

28.3.2.2

860

0 12345678910111213 15

861

28.3.1.4

862

Figure 28-7. INTMSK Mask Bits

863

28-18 Freescale Semiconductor

866

0 3 4 5 6 7 8 9 10 11 12 15

872

Figure 28-11. Mask1 Format

874

Figure 28-12. Mask2 Format

874

Freescale Semiconductor 28-27

875

28.4 Channel Extra Parameters

876

28.5 Superchannels

877

28-30 Freescale Semiconductor

878

28.7 MCC Commands

882

28.8 MCC Exceptions

883

0 1 2 3 4 5 6 7 8 1112 131415

885

Freescale Semiconductor 28-41

889

28.9 MCC Buffer Descriptors

891

Invalid data

893

28-48 Freescale Semiconductor

896

Freescale Semiconductor 28-49

897

28-50 Freescale Semiconductor

898

Chapter 29

899

29-2 Freescale Semiconductor

900

29.6 FCC Buffer Descriptors

907

+ 0 Status and Control

908

29.7 FCC Parameter RAM

909

29.8 Interrupts from the FCCs

912

29.9 FCC Initialization

913

29.10 FCC Interrupt Handling

914

29.11 FCC Timing Control

915

Figure 29-10. CTS Lost

917

Freescale Semiconductor 29-21

919

29.13 Saving Power

920

Chapter 30

921

ATM Controller and

921

AAL0, AAL1, and AAL5

921

30-2 Freescale Semiconductor

922

Freescale Semiconductor 30-3

923

30.2 ATM Controller Overview

924

30.2.1 Transmitter Overview

925

30.2.2 Receiver Overview

926

Freescale Semiconductor 30-7

927

30.2.3 Performance Monitoring

928

30.2.4 ABR Flow Control

928

Max bit rate =

930

30.3.5 ATM Traffic Type

931

Freescale Semiconductor 30-13

933

30.4.1 External CAM Lookup

934

30.4.2 Address Compression

935

30.4.3 Misinserted Cells

938

30.4.4 Receive Raw Cell Queue

938

30.5.1 The ABR Model

940

30.5.1.3 ABR Flowcharts

941

30.5.2 RM Cell Structure

945

012 67 15

946

30.6 OAM Support

947

30.6.6 Performance Monitoring

949

30.6.6.2 PM Block Monitoring

950

30.6.6.3 PM Block Generation

951

30.7 User-Defined Cells (UDC)

952

30.8 ATM Layer Statistics

953

30.9 ATM-to-TDM Interworking

953

30.9.3 Timing Issues

955

30.9.6 CAS Support

955

30.10 ATM Memory Structure

956

30.10.2.1 ATM Channel Code

961

+ 0x0E TML

966

Freescale Semiconductor 30-51

971

30-52 Freescale Semiconductor

972

0 7 8 9 10 11 12 15

977

— 0 CR10 — ACHC —

977

+ 0x12 —

977

30.10.4 APC Data Structure

983

30.10.4.2 APC Priority Table

985

Figure 30-40. Control Slot

986

Buffer 3 of FBP1

989

Free Buffer Pool 1

989

01234 15

990

30.10.5.4 AAL5 RxBD

991

30.10.5.5 AAL1 RxBD

993

30.10.5.6 AAL0 RxBD

994

30.10.5.7 AAL1 CES RxBD

995

30.10.5.8 AAL2 RxBD

995

30.10.5.10 AAL5 TxBDs

996

30.10.5.11 AAL1 TxBDs

997

30.10.5.12 AAL0 TxBDs

998

30.10.5.13 AAL1 CES TxBDs

999

30.10.5.14 AAL2 TxBDs

1000

30.11 ATM Exceptions

1001

30.11.2 Interrupt Queue Entry

1002

Name Description

1003

30.12 The UTOPIA Interface

1004

30.13 ATM Registers

1007

0 3 4 7 8 9 10 11 15

1008

(FCC1 and FCC2 Only)

1011

Table 30-49. FTIRR

1012

Field Descriptions

1012

30.14 ATM Transmit Command

1013

30.16.2 APC Configuration

1016

30.16.3 Buffer Configuration

1016

Chapter 31

1017

31-2 Freescale Semiconductor

1018

31.2.1 Data Path

1019

31.2.2 Signaling Path

1019

Freescale Semiconductor 31-5

1021

31.4 Interworking Functions

1022

31.4.1.1 ATM-to-TDM

1023

31.4.1.2 TDM-to-ATM

1023

31.4.2 Timing Issues

1024

Freescale Semiconductor 31-9

1025

31.4.5 Trunk Condition

1026

31.4.7.1 CAS Routing Table

1028

Freescale Semiconductor 31-15

1031

31.6 3-Step-SN Algorithm

1036

31.8 AAL-1 Memory Structure

1038

(RCT, TCT)

1041

Bits Name Description

1043

+ 0x16 Block Size

1045

01234567 8 91011 12 131415

1047

command is needed, which

1048

command. When the host

1048

31.11 Buffer Descriptors

1052

TBD_Base

1053

Pointers

1053

31.12 ATM Controller Buffers

1054

Figure 31-28. AAL1 CES RxBD

1055

31.12.2 AAL1 CES TxBDs

1056

31.13 AAL1 CES Exceptions

1057

Figure 31-31

1058

ATM_CHANNEL# × 8

1059

Width Description

1060

31-46 Freescale Semiconductor

1062

Chapter 32

1063

ATM AAL2

1063

32.2 Features

1065

32-4 Freescale Semiconductor

1066

32.3 AAL2 Transmitter

1067

32.3.2.1 Round Robin Priority

1068

32.3.2.2 Fixed Priority

1068

32.3.4 No STF Mode

1070

32-10 Freescale Semiconductor

1072

Field Descriptions

1073

32.3.5.3 CPS Buffer Structure

1077

Figure 32-9. CPS TxBD

1078

Figure 32-12. SSSAR TxBD

1081

32.4 AAL2 Receiver

1082

Freescale Semiconductor 32-21

1083

32.4.3 AAL2 Switching

1084

Figure 32-14. AAL2 Switching

1085

32.5 AAL2 Parameter RAM

1097

32.7 AAL2 Exceptions

1100

Chapter 33

1103

33.1.1 References

1105

33.1.2 IMA Versions Supported

1105

33.2 IMA Protocol Overview

1106

33.2.2 IMA Frame Overview

1107

33.2.3 Overview of IMA Cells

1109

33.2.3.2 IMA Filler Cells

1112

33.3.2 Transmit Architecture

1113

33.3.2.1 TRL Operation

1114

33.3.2.2 Non-TRL Operation

1115

33.3.3 Receive Architecture

1119

33-18 Freescale Semiconductor

1120

Cell Reception Task

1121

33-20 Freescale Semiconductor

1122

Freescale Semiconductor 33-21

1123

33-22 Freescale Semiconductor

1124

Freescale Semiconductor 33-23

1125

33.4 IMA Programming Model

1126

1MByte Boundary

1127

External memory

1127

(Local or 60x Bus)

1127

33.4.2 IMA FCC Programming

1128

33.4.3 IMA Root Table

1129

Table 33-3. IMA Root Table

1130

(continued)

1130

33.4.4 IMA Group Tables

1131

Name Width Description

1132

0 234567

1133

01234567

1134

Table 33-9. ICP Cell Template

1135

33.4.5 IMA Link Tables

1143

012345 7

1144

0 12 3 4567

1149

8 9 10 11 12 13 14 15

1149

33.4.6.1 Transmit Queues

1150

33.4.7 IMA Exceptions

1151

33-50 Freescale Semiconductor

1152

OFFSET + 2 L/G NUM

1152

33.4.8 IDCR Timer Programming

1154

Freescale Semiconductor 33-53

1155

33.4.8.3 IDCR_Init Command

1156

33.4.8.4 IDCR Root Parameters

1156

33.4.8.5 IDCR Table Entry

1156

33.4.8.7 IDCR Events

1157

33.4.9.2 Programming for ABR

1159

33.4.10 Changing IMA Version

1160

33.5.1 Software Model

1160

33.5.3.1 System Definition

1161

33.5.3.2 General Operation

1162

33.5.3.10 Failure Alarms

1163

33.5.3.13 SNMP MIBs

1164

Freescale Semiconductor 33-63

1165

33-64 Freescale Semiconductor

1166

33-66 Freescale Semiconductor

1168

Freescale Semiconductor 33-67

1169

33-68 Freescale Semiconductor

1170

Freescale Semiconductor 33-69

1171

33-70 Freescale Semiconductor

1172

Freescale Semiconductor 33-71

1173

33-72 Freescale Semiconductor

1174

33.5.4.12 IDCR Operation

1175

33-74 Freescale Semiconductor

1176

33.5.4.13.2 Receive

1177

33-76 Freescale Semiconductor

1178

Chapter 34

1179

34-2 Freescale Semiconductor

1180

34.2 Functionality

1181

34-4 Freescale Semiconductor

1182

PowerQUICC II

1182

34.3 Signals

1185

0 1 23456789101112131415

1186

Table 34-3. CDSMR

1187

Table 34-4. TCER

1188

012345678 15

1189

34.4.3 TC Layer Cell Counters

1190

34.4.4 Programming FCC2

1191

34.5 Implementation Example

1193

Table 34-8. Enable FCC2

1195

Chapter 35

1197

Fast Ethernet Controller

1197

35.2 Features

1198

Freescale Semiconductor 35-3

1199

GRACEFUL STOP

1201

RESTART TRANSMIT

1202

35.6 Flow Control

1203

35.7 CAM Interface

1203

35.8 Ethernet Parameter RAM

1204

35.9 Programming Model

1207

35.10 Ethernet Command Set

1207

Table 35-3. Transmit Commands

1208

Table 35-4. Receive Commands

1208

35.11 RMON Support

1209

35.13 Hash Table Algorithm

1212

35.14 Interpacket Gap Time

1213

35.15 Handling Collisions

1213

35.18 Fast Ethernet Registers

1214

35.19 Ethernet RxBDs

1218

35.20 Ethernet TxBDs

1221

35-28 Freescale Semiconductor

1224

Chapter 36

1225

FCC HDLC Controller

1225

STOP TRANSMIT command

1226

RESTART TRANSMIT command, it

1226

GRACEFUL

1226

36.4 HDLC Parameter RAM

1227

36.5 Programming Model

1229

36.5.2 HDLC Error Handling

1230

Figure 36-3

1231

“Parallel I/O Ports.”

1240

36-18 Freescale Semiconductor

1242

Chapter 37

1243

FCC Transparent Controller

1243

Freescale Semiconductor 37-3

1245

Chapter 38

1247

38-2 Freescale Semiconductor

1248

38-4 Freescale Semiconductor

1250

— 0_0000_0000

1252

(SPMODE[CP] = 1)

1253

NOTE: Q = Undefined Signal

1254

38.5 SPI Parameter RAM

1256

38.6 SPI Commands

1258

INIT RX

1259

PARAMETERS

1259

Figure 38-11. SPI RxBD

1260

Figure 38-12

1261

Freescale Semiconductor 38-17

1263

38-18 Freescale Semiconductor

1264

Chapter 39

1265

C Controller

1265

39.1 Features

1266

C Controller Transfers

1266

39.3.1 I

1267

C Master Write (Slave Read)

1267

39.3.2 I

1268

C Loopback Testing

1268

39.3.3 I

1268

C Master Read (Slave Write)

1268

39.3.4 I

1269

C Multi-Master Considerations

1269

C Registers

1270

39.4.3 I

1271

39.4.4 I

1271

39.4.5 I

1272

C Command Register (I2COM)

1272

C Parameter RAM

1273

Figure 39-11. I

1274

Table 39-6. I

1274

C Commands

1275

39.7 The I

1275

39.7.1 I

1276

C Buffer Descriptors (BDs)

1276

39.7.1.2 I

1277

Table 39-10 describes I

1278

Chapter 40

1279

Parallel I/O Ports

1279

Table 40-1. PODR

1280

40.3 Port Block Diagram

1283

40.4 Port Pins Functions

1284

40.5 Ports Tables

1285

40.6 Interrupts from Port C

1297

40-20 Freescale Semiconductor

1298

Appendix A

1299

A.3 MPC8260-Specific SPRs

1301

A-4 Freescale Semiconductor

1302

Appendix B

1303

B-4 Freescale Semiconductor

1306

Freescale Semiconductor B-7

1309

66MHz 53 8×()×()

1313

155.52Mbps

1313

30 with the

1314

B-14 Freescale Semiconductor

1316

B-16 Freescale Semiconductor

1318

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