
Programmer’s Reference
DSP56364 24-Bit Digital Signal Processor Users Manual, Rev. 2
Freescale Semiconductor C-5
Reserved $FFFF9F thru $FFFF95 RESERVED
SHI $FFFF94 SHI RECEIVE FIFO (HRX)
$FFFF93 SHI TRANSMIT REGISTER (HTX)
$FFFF92 SHI I
2
C SLAVE ADDRESS REGISTER (HSAR)
$FFFF91 SHI CONTROL/STATUS REGISTER (HCSR)
$FFFF90 SHI CLOCK CONTROL REGISTER (HCKR)
Reserved $FFFF8F thru $FFFF80 RESERVED
Table C-2. DSP56364 Interrupt Vectors
Interrupt
Starting Address
Interrupt Priority
Level Range
Interrupt Source
VBA:$00 3 Hardware RESET
VBA:$02 3 Stack Error
VBA:$04 3 Illegal Instruction
VBA:$06 3 Debug Request Interrupt
VBA:$08 3 Trap
VBA:$0A 3 Non-Maskable Interrupt (NMI)
VBA:$0C 3 Reserved For Future Level-3 Interrupt Source
VBA:$0E 3 Reserved For Future Level-3 Interrupt Source
VBA:$10 0 - 2 IRQA
VBA:$12 0 - 2 IRQB
VBA:$14 0 - 2 Reserved
VBA:$16 0 - 2 IRQD
VBA:$18 0 - 2 DMA Channel 0
VBA:$1A 0 - 2 DMA Channel 1
VBA:$1C 0 - 2 DMA Channel 2
VBA:$1E 0 - 2 DMA Channel 3
VBA:$20 0 - 2 DMA Channel 4
VBA:$22 0 - 2 DMA Channel 5
VBA:$24 0 - 2 Reserved
VBA:$26 0 - 2 Reserved
VBA:$28 0 - 2 Reserved
VBA:$2A 0 - 2 Reserved
VBA:$2C 0 - 2 Reserved
Table C-1. Internal I/O Memory Map (continued)
Peripheral Address Register Name
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